Military and commercial computing, communication and navigation products often require high speed encryption and decryption of data. Commonly assigned, non-provisional U.S. patent application Ser. No. 10/616,199, filed Jul. 9, 2003, entitled “Method And System For Cryptographic Processing” and listing as inventors D. Jensen, M. Bortz, and T. MacDonald describes the Programmable Cryptography Processor (PCP) architecture developed by Rockwell Collins to address the security needs of several military products. The PCP provides a fully configurable, non-classified encryption core that supports a variety of legacy and modern algorithms.
Future systems using modern algorithms may have agility and throughput requirements greater than the current capabilities of the PCP design. In addition, continuing advances in algorithmic complexity and security levy strong requirements on the development of next-generation encryption hardware development.
The PCPr0 available from Rockwell Collins of Cedar Rapids, Iowa is an exemplary high performance, general-purpose, cryptographic processor developed from the concepts outlined in the referenced PCP U.S. patent application Ser. No. 10/616,199. The microarchitecture of the PCP processing core provides an engine that can perform many different modern and legacy cryptographic algorithms: AES, Medley, Keesee, Shillelagh, Saville, etc. The microcode loaded into the device control store memory defines which algorithms are currently supported.
In exchange for the configurability and flexibility to support many different algorithms, the architecture is limited in its number of configuration blocks. The conventional PCP architecture is designed to support one algorithm at a time, meaning a configuration loaded into the device contains all information needed to execute only that single algorithm. Accordingly, there is a need to modify the current PCP architecture to provide algorithm agility, which is the support for multiple concurrent algorithms using a single configuration load. In addition, there is a need for the ability to take existing single algorithm implementations and combine them into a concurrent algorithm implementation without requiring a recompile of the algorithm code. Finally, there is a need for supporting the functionality to switch algorithms on word boundaries.
The techniques herein below extend to those embodiments which fall within the scope of the appended claims, regardless of whether they accomplish one or more of the above-mentioned needs.